NVIDIA Locks In Samsung and SK Hynix in Dual Memory Partnerships as AI Factory Buildout Accelerates
Two Deals, One Strategic Throughline
NVIDIA has formalized separate, far-reaching partnerships with SK Hynix and Samsung — the two dominant players in high-bandwidth memory — as it works to secure the memory supply chain underpinning its next-generation AI infrastructure platforms. The arrangements go well beyond conventional supplier agreements, pulling both Korean chipmakers into co-development, manufacturing optimization, and silicon design workflows directly tied to NVIDIA's roadmap.
The scope is substantial on both sides. With SK Hynix, the deal is a multiyear technology partnership structured around codeveloping memory for four distinct NVIDIA platforms: the Vera Rubin AI supercomputer, the Vera CPU, RTX Spark-powered PCs, and the Jetson Thor robotic computing platform — covering the data center, edge, and robotics segments of NVIDIA's portfolio simultaneously. With Samsung, the arrangement is oriented around manufacturing intelligence: a new AI Megafactory that will deploy more than 50,000 NVIDIA GPUs across Samsung's semiconductor operations, integrating design, process control, equipment management, operations, and quality assurance into a single intelligent network. Source: NVIDIA Newsroom | Source: Samsung Newsroom
SK Hynix: From Supplier to Co-Developer
The SK Hynix partnership moves the relationship from transactional to architectural. Codeveloping memory for Vera Rubin — NVIDIA's next-generation AI supercomputer platform — means SK Hynix engineers are working on HBM specifications in parallel with NVIDIA's system architects rather than responding to them after the fact. That distinction matters: when memory bandwidth and latency targets are set jointly at the platform design stage, the resulting silicon is more tightly optimized than off-the-shelf HBM stacked onto a compute die post-design.
SK Hynix also announced it is using NVIDIA's CUDA-X libraries and AI-driven tooling to accelerate its own semiconductor simulation workflows, specifically technology computer-aided design (TCAD) and computational lithography. Source: NVIDIA Newsroom These are not peripheral processes. TCAD governs how a fab models carrier transport through transistor structures before committing to physical process steps; computational lithography determines how photomask patterns are corrected to account for diffraction and etch effects at advanced nodes. Accelerating both with GPU-driven simulation compresses process development cycles — which, at 5nm and below, can run to years and hundreds of millions of dollars per node iteration.
SK Hynix began mass production of its then-next-generation HBM chips in March 2024, an early mover advantage that helped cement its position as NVIDIA's primary HBM3E supplier ahead of the H100 and H200 ramp. Source: Reuters The new partnership formalizes and deepens a relationship that was already generating meaningful revenue.
Samsung: GPUs on the Fab Floor
Samsung's AI Megafactory initiative is a different kind of engagement — less about memory architecture, more about using NVIDIA's compute stack to transform how Samsung manufactures semiconductors at scale.
Deploying 50,000 GPUs across memory, logic, foundry, and advanced packaging lines is an infrastructure commitment of the order typically associated with hyperscale cloud build-outs, not semiconductor fabs. Samsung plans to scale the AI Factory using NVIDIA accelerated computing alongside NVIDIA Omniverse libraries — the latter providing a physics-accurate digital twin layer capable of modeling fab equipment, process flows, and logistics in real time. Source: Samsung Newsroom
Samsung is also pushing forward on memory architecture independent of the NVIDIA partnership. The company has unveiled HBM-PIM — processing-in-memory technology that embeds compute logic directly within HBM stacks to reduce data movement for hyperscale AI inference workloads. Paired with CXL-PNM (Compute Express Link Processing Near Memory) solutions, Samsung is positioning an HBM-PIM Cluster architecture aimed at high-efficiency memory fabric for large model inference. Source: Samsung Semiconductor On the supply side, Samsung planned to begin HBM4 production in February 2026, targeting NVIDIA supply — a critical milestone given how far it lagged SK Hynix in HBM3E qualification. Source: Reuters
Why NVIDIA Is Doing This Simultaneously
The parallel nature of these two partnerships is not incidental. NVIDIA's demand for HBM is structural and accelerating — every Blackwell GPU ships with HBM3E, and Vera Rubin will require HBM4 at scale. A single-supplier dependency at that volume would be a procurement and geopolitical liability, particularly given the concentration of advanced HBM production on the Korean peninsula.
We have seen this dynamic play out before in semiconductor supply chains. In the early 2010s, Apple's aggressive multi-sourcing of DRAM and NAND — spreading contracts across Samsung, SK Hynix, and Micron — gave it both pricing leverage and supply resilience that single-source rivals lacked when spot shortages hit. NVIDIA is constructing a structurally similar hedge, but with a twist: rather than simply spreading purchase orders, it is embedding its own technology — CUDA-X, Omniverse, TCAD acceleration tooling — into both partners' R&D and manufacturing infrastructure. That creates switching costs on both sides. SK Hynix and Samsung become more capable the longer they run on NVIDIA's tools; NVIDIA gains visibility into process development timelines that no purchase agreement alone would provide.
The Memory Architecture Inflection
What ties these announcements together is a broader transition in how the industry thinks about memory in AI systems. For most of the past decade, HBM was treated as a bandwidth solution: stack DRAM dies on an interposer next to the GPU, connect them via a wide through-silicon via interface, ship more GB/s to the compute die. The HBM-PIM work Samsung is advancing, and the tight platform co-development SK Hynix is undertaking for Vera Rubin, both signal that memory is evolving into an active participant in compute rather than a passive substrate.
PIM architectures push a portion of the arithmetic — particularly reduction and activation operations common in transformer inference — into the memory stack itself, cutting the energy cost of moving data to the GPU and back. At the power envelopes that large AI clusters now operate at — facilities drawing hundreds of megawatts — even marginal reductions in data movement energy compound meaningfully across tens of thousands of accelerators.
What This Means for the Competitive Landscape
For Micron, the only non-Korean HBM producer of scale, the depth of these bilateral partnerships raises the bar on what "qualified supplier" means in NVIDIA's ecosystem. Shipping HBM4 on spec is necessary but may not be sufficient if SK Hynix and Samsung are co-designing to the platform from the ground up.
For the foundry and advanced packaging segments — particularly TSMC and the emerging CoWoS supply chain — the Samsung AI Megafactory's integration of NVIDIA Omniverse across packaging infrastructure is a signal that fab intelligence is becoming a competitive differentiator, not just a cost-reduction tool. If Samsung can demonstrably compress cycle time or improve yield through AI-driven process control, it changes the calculus for customers evaluating foundry partners.
And for the broader AI infrastructure supply chain, these announcements collectively mark a phase shift: the world's largest accelerator maker is no longer simply specifying what it wants from memory suppliers — it is co-building the tools those suppliers use to design and manufacture it.
