NVIDIA Sets Concrete Requirements for Running CUDA on RISC-V Server CPUs
At Hot Chips 2026, held August 23–25 at Stanford University's Memorial Auditorium in Palo Alto, NVIDIA laid out the technical requirements for extending its CUDA software platform to RISC-V CPUs. The effort formalizes a compatibility plan first announced at the 2025 RISC-V Summit in China, where NVIDIA said CUDA would be made to work with the RISC-V instruction set alongside existing x86-64 and ARM support (RISC-V International).
CUDA is NVIDIA's software layer for programming GPUs — it lets developers write code that runs on NVIDIA's graphics processors for tasks like AI training, scientific simulation, and other compute-heavy workloads. RISC-V is an open instruction set architecture, meaning anyone can implement it without paying licensing fees, unlike x86 (controlled by Intel and AMD) or ARM (licensed from Arm Holdings). Until now, CUDA has only run on x86 and ARM host CPUs.
The requirements NVIDIA specified are narrow and demanding. RISC-V CPUs must conform to the RVA23 profile, which is a standardized bundle of RISC-V features that ensures software compatibility across different chipmakers' implementations. They must also comply with the RISC-V server SoC (system-on-chip) and server platform specifications. On the interconnect side, NVIDIA requires support for PCIe coherency — meaning the CPU and connected devices like GPUs can share a consistent view of memory — and peer-to-peer PCIe communication, which lets devices talk to each other directly without routing through the CPU. Together, these requirements define a fairly narrow class of server-grade RISC-V silicon that can participate in CUDA-accelerated workloads. Consumer or embedded RISC-V parts need not apply (Chips and Cheese).
The platform infrastructure for RISC-V in server contexts has been maturing in parallel. In 2025, the UEFI Forum added RISC-V ACPI support. ACPI (Advanced Configuration and Power Interface) is the standard an operating system uses to discover and manage hardware devices at boot. The RISC-V BRS (Boot and Runtime Services) specification was also ratified in 2025, with ACPI included. These specifications cover the boot and device-enumeration layers that an operating system and a runtime like CUDA depend on when targeting a new instruction set in a server environment. Their ratification removed a category of infrastructure gaps that would otherwise have made a CUDA port to RISC-V impractical (Chips and Cheese).
NVIDIA also presented requirements for NVLink Fusion at the conference. NVLink Fusion allows third-party chip designers to license and implement NVIDIA's NVLink interconnect — the high-speed data link NVIDIA uses to connect its GPUs to each other and to host CPUs — on their own silicon. Pairing an open NVLink licensing model with CUDA-on-RISC-V support creates a path by which a RISC-V server chip vendor could, in principle, build a coherent accelerator platform using NVIDIA's interconnect and software stack without relying on x86 or ARM as the host CPU (Chips and Cheese).
NVIDIA's engagement with RISC-V is not entirely new. At Hot Chips 34 in 2022, NVIDIA presented its Hopper GPU architecture, which incorporated more than 1,000 RISC-V cores as embedded controllers on the GPU die itself. That design used RISC-V for fine-grained, on-chip management tasks — a domain where the instruction set's extensibility and lack of licensing overhead offered practical advantages. The CUDA-on-RISC-V effort targets a different layer entirely: the host CPU running the CUDA runtime, dispatching compute kernels, and managing memory across the PCIe or NVLink fabric.
The broader context here is the maturation of RISC-V as a server-class instruction set. The RVA23 profile, the server SoC and platform specifications, the BRS ratification, and UEFI ACPI support collectively form the stack of standards a data-center-class RISC-V platform needs to interoperate with established system software. NVIDIA's CUDA requirements effectively consume that stack, specifying which RISC-V profiles and platform features a system must implement to be a valid CUDA host.
Worth flagging is the combination of CUDA portability and NVLink Fusion. Individually, each broadens NVIDIA's ecosystem in a different direction: CUDA reaches a new instruction set, and NVLink reaches beyond NVIDIA's own silicon. Taken together, they sketch an architecture in which a third-party RISC-V server CPU with a licensed NVLink controller could serve as a first-class host for NVIDIA GPUs, running CUDA workloads over a coherent fabric. Whether any RISC-V vendor currently ships hardware meeting all of these requirements is not something NVIDIA addressed in the presentation as reported. The requirements set the bar; the silicon has to clear it.
Hot Chips 2026 presentation slides are posted daily at 7:00 AM PDT, and in-person attendance for the conference is sold out (Hot Chips). NVIDIA is using its Hot Chips 2026 participation to showcase its Accelerated Computing platform for AI data centers (NVIDIA).
For RISC-V proponents, the CUDA requirements offer a concrete target rather than aspirational language. The RVA23 profile, server platform compliance, PCIe coherency, and peer-to-peer PCIe together define a checklist that turns the idea of CUDA on RISC-V from a summit-stage announcement into an engineering specification. How quickly RISC-V server silicon arrives that meets every item on that checklist will determine whether CUDA workloads run on open-ISA hosts in production at any scale in the near term.
