Google Adds TPU 8tx and TPU 8i Max, Extending Its Eighth-Generation Split by Workload

Google has unveiled two new Tensor Processing Units, the TPU 8tx and the TPU 8i Max, according to a TechCrunch report published November 10, 2026. Both belong to the eighth generation of TPUs, which Google introduced in April 2026.

The TPU 8tx is based on the TPU 8t and was designed with AMD. It targets confidential training and the running of AI models. Security is built into the hardware layer, with the goal of keeping data and model weights (the learned parameters that define a model) protected and isolated while they are in active use.

The chip also includes a custom inferencing network. According to the report, it can run reasoning alongside training, including distilling and training small models on the fly. Distillation means training a smaller model to reproduce the behaviour of a larger one.

The TPU 8i Max packages two inference-focused TPU 8i chips, launched in April, into a single unit. The combination doubles memory capacity, processing power and bandwidth.

The mix of variants is the notable part. Google's eighth generation already split the lineup by workload, and the new parts extend that split in two directions. The 8tx targets training, with the added requirement of confidentiality. The 8i Max targets inference, scaling one inference chip into a denser package rather than introducing a new architecture. Teams building on TPUs now have more options for matching a part to a workload.

In my view, the confidentiality angle deserves the closest reading. Protecting model weights and data during active computation moves part of the trust boundary into the silicon itself. For organizations training or serving proprietary models, the question shifts from whether to trust a cloud provider's isolation to whether a hardware-enforced isolation model meets their threat assumptions. Those assumptions differ by sector and by regulatory regime, and no single announcement settles them.

The design partner also matters. AMD is a direct competitor in accelerator silicon, so a co-designed TPU variant is an unusual arrangement to see announced publicly. The broader context here is that the accelerator market has been moving toward heterogeneous stacks, where hyperscalers mix in-house silicon with merchant parts. A jointly designed chip is one way to make that mixing less of a compromise.

The on-the-fly distillation capability is worth watching for a different reason. If one system can run reasoning and train small models while a larger training job proceeds, the boundary between training and serving starts to blur. That could shorten the loop between a frontier model and the smaller models derived from it. It also raises the operational question of how that concurrent work is scheduled and isolated on shared hardware.

The announcement describes design claims and capabilities. Real-world adoption will depend on availability, pricing and benchmark results from customers running these chips in production. For engineers already working with TPUs, the practical value of the 8tx and 8i Max will be settled by those measurements. For everyone else, the more useful signal is the direction: accelerators are being specialized along lines of confidentiality, reasoning-plus-training, and dense inference. That specialization is likely to shape how AI workloads are placed across cloud infrastructure in the years ahead.