Samsung has unveiled concept models for zHBM, a memory design that vertically stacks high-bandwidth memory (HBM) directly on top of AI accelerators, at the Future of Memory and Storage (FMS) 2026 show in Santa Clara. The announcement, reported on August 4, 2026 by both Samsung's newsroom and Reuters, lays out what Samsung calls a fundamentally new approach to 3D memory stacking for AI data centers.

To understand why this matters, a quick orientation: HBM is a type of memory built in stacked layers that sits close to a processor to deliver very high data throughput. Today, HBM and the AI accelerator (the chip doing the heavy math) are placed side by side on a small circuit board called an interposer. zHBM eliminates that horizontal gap by bonding the memory stack directly on top of the accelerator die — imagine moving from a suburban layout where two buildings sit across a parking lot from each other to a high-rise where they occupy the same footprint.

Samsung claims zHBM boosts performance by up to eight times compared to existing HBM arrangements. The architecture uses next-generation wafer bonding technology — a manufacturing process that fuses entire silicon wafers together — enabling over 10 times the memory density of current HBM5 tech, and Samsung reports a threefold increase in energy efficiency. The company presented these as concept models, not production-ready products. Engadget, publishing August 5, 2026, provided the detailed specifications.

Alongside zHBM, Samsung introduced V10 BV-NAND, a V-NAND memory type built with its new bonding V-NAND architecture for use in SSDs, memory cards, and other storage. V-NAND is Samsung's brand of 3D flash memory, where memory cells are stacked vertically in layers rather than laid flat on a single plane — think of it as building upward instead of outward. V10 BV-NAND stacks more than 400 layers of memory cells and increases memory density by approximately 58 percent over the previous V9 generation. Samsung claims it boosts read, write, and I/O performance across the board.

Samsung also unveiled zNAND-O, a next-generation V-NAND solution aimed at edge AI environments — that is, AI processing done on devices like phones, cars, and sensors rather than in a centralized data center. It combines high space efficiency, improved I/O performance, and low latency. The company showcased LPDDR5X-PIM at the booth as well, describing it as the industry's first LPDDR memory with processing-in-memory technology. Processing-in-memory, or PIM, is an approach where small computing operations happen inside the memory chip itself, reducing the need to shuttle data back and forth to a CPU. Samsung's FMS 2026 presence featured an AI cloud server-inspired booth displaying approximately 30 memory and storage technologies.

The FMS 2026 unveilings arrive against a financial backdrop that tells you how much demand is driving these architectures. Samsung's second-quarter 2026 operating profit jumped 19-fold year on year, with chip profit rising more than 250-fold to $61.7 billion, Reuters reported on July 30, 2026. The company announced multi-year supply deals with major data center operators extending into 2028 and sees the memory chip shortage extending to that same year. In March 2026, Samsung's CEO sought multi-year chip supply contracts with major operators, pushing shares to record highs. Samsung also began shipping samples of its latest high-bandwidth memory chip to customers in June 2026.

The trajectory from Samsung's earlier V-NAND work to the FMS 2026 concepts is steep. The company started mass-producing its first 32-layer 3D V-NAND in 2014, reached 48 layers with 256-gigabit 3-bit MLC flash in 2015, and introduced sixth-generation V-NAND for client computing in 2019. Each generation roughly doubled layer counts. V10 BV-NAND's 400-plus layers sit near the architectural endpoint of that scaling curve, and the shift to bonding V-NAND suggests Samsung is moving beyond purely vertical stacking into wafer-level integration as the path to further density gains.

The broader context here is that the AI accelerator memory bottleneck is no longer just about bandwidth per package. It is about the physical distance between compute and memory, the power cost of moving data across that distance, and the packaging density achievable within a data-center footprint. zHBM's claimed 8x performance and 3x energy efficiency, if realized in silicon, would address all three of those vectors simultaneously by collapsing the interposer-and-substrate path between HBM and the accelerator die into a bonded vertical stack. The wafer bonding technology enabling over 10x density over HBM5 is the critical enabler, and it is the component most likely to face manufacturing yield challenges at scale — yield being the percentage of chips that come out of a production line working correctly.

Worth flagging that Samsung is presenting these as concept models, not product roadmaps with delivery dates. The gap between a concept demo at FMS and volume production of bonded 3D stacks could be measured in years. The company's own projection that memory shortages extend to 2028 sets a timeline that is both a supply constraint and a commercial incentive to move these architectures into production as fast as yield curves allow.

The LPDDR5X-PIM introduction is the quieter announcement with potentially the broadest reach. Processing-in-memory has been a research topic for over a decade; bringing it into an LPDDR package targets edge and mobile AI workloads where the power cost of data movement between CPU and memory dominates. Samsung's positioning of zNAND-O for edge AI environments reinforces a clear product strategy: data-center architectures get vertical HBM stacking, edge gets PIM and low-latency V-NAND.

Samsung's V-NAND-based SSDs have historically delivered approximately twice the write endurance and 20 percent lower power consumption compared to planar memory, advantages that carried flash into data centers as it displaced hard disk drives. Flash memory is now the default storage medium in that segment. V10 BV-NAND's 58 percent density gain over V9 keeps that cost-per-bit curve descending, which matters for the storage tier of AI infrastructure even as zHBM targets the compute-adjacent memory tier.

The FMS 2026 announcements collectively sketch a memory architecture stack that spans from data-center AI accelerators down to edge devices, unified by bonding and vertical stacking as the shared manufacturing approach. Samsung's financial results and supply contracts through 2028 provide the commercial engine to fund the transition from concept to production.