Ricursive Intelligence Wants AI to Design Whole Chips in a Week

Ricursive Intelligence is building AI that designs chips and improves with each chip it designs.

Anna Goldie and Azalia Mirhoseini founded the company and introduced it on stage at TechCrunch Disrupt. The stated goal is automating and speeding up the chip design process TechCrunch. Goldie is listed as founder and CEO Ricursive Intelligence. The company describes itself as a frontier AI lab building self-improving systems, starting with chip design, and lists ricursive.com as its official website Ricursive Intelligence.

Goldie said demand for compute will grow at least 10,000 times in the next five years. She said more efficient chips that make better use of data-center bandwidth, wafers (the silicon discs chips are cut from) and fabs (the factories that build chips) could meet that demand without building 10,000 times more data centers. She said if AI takes over design execution, people can spend more time building applications and trying new ideas.

On method, Ricursive optimizes a whole chip at once instead of splitting it into dozens of smaller blocks. Goldie and Mirhoseini previously built AlphaChip, an AI system that placed chip components in a circular, donut-like layout. Goldie said cutting design time to about a week, down from six months to two years, would make custom chips for space, AR, VR and biological computing financially viable.

The broader context here is scope and repetition, and they work differently. Designing the full chip keeps tradeoffs across the whole design in view. Splitting into blocks makes the problem smaller but hides how choices in one block affect another. A system that learns across runs is betting that shared memory can handle the larger problem, so progress compounds from project to project.

A familiar pattern is also at work in how the work is divided. Detailed execution is slow and repetitive. Exploration is open ended. When reliable automation takes over execution, engineers spend more time on architecture, interfaces and what applications need. We have seen this before when higher-level tools let engineers focus less on manual detail and more on intent.

In my view, the hard questions are practical, not conceptual. A chip passes through many stages, many teams and shifting constraints. Testing has to stay consistent enough to learn from and still match final signoff, the last checks before manufacturing. Training data has to be broad enough to apply elsewhere without carrying over details that do not transfer. The tools have to fit into daily work. None of that argues against the approach. It shows where progress will be slow and where it could move fast.

Looking further out, the payoff could be wider access to custom silicon. Long cycles punish small production runs. Short cycles lower the bar for what gets built. Hardware for niche settings and experimental interfaces becomes easier to justify. More teams get to test more ideas in real silicon.